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| ADVANCE INFORMATION CY26049-4 FailSafeTM PacketClockTM Global Communications Clock Generator Features * Fully integrated phase-locked loop (PLL) * FailSafe output * PLL driven by a crystal oscillator that is phase aligned with external reference * 35.328-MHz output from 19.44-MHz input * Low-jitter, high-accuracy outputs * 3.3V 5% operation * 16-lead TSSOP Benefits * Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external loop filter components * When reference is off, DCXO maintains clock outputs and SAFE pin indicates FailSafe conditions * DCXO maintains continuous operation should the input reference clock fail * Glitch-free transition simplifies system design * FailSafe DCXO loop bandwidth approximately 100Hz * Works with commonly available, low-cost 19.44-MHz crystal * Zero-ppm error for all output frequencies * Compatible across industry standard design platforms * Industry standard package with 6.4 x 5.0 mm2 footprint and a height profile of just 1.1 mm Logic Block Diagram external pullable crystal (19.44M H z) X IN input reference (19.44M H z) IC LK FA ILS A FETM C O N TR O L D IG ITA L C O N TR O LLE D C R Y S TA L O S C ILLA TO R PHASE LO C K E D LO O P C LK A 35.328 M H z XOUT O U TP U T D IV ID E R S A FE IC LK detected Cypress Semiconductor Corporation Document #: 38-07484 Rev. *A * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised September 5, 2003 ADVANCE INFORMATION Pin Configuration CY26049-4 16-pin TSSOP Top View ICLK 1 NC NC NC 2 3 4 16 NC 15 NC 14 NC 13 NC 12 VDD 11 VSS 10 SAFE 9 XOUT CY26049-4 VDD 5 VSS 6 CLKA 7 XIN 8 Pin Description Pin Number Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ICLK NC NC NC VDD VSS CLKA XIN XOUT SAFE VSS VDD NC NC NC NC Reference Input Clock; 19.44 MHz. No Connect. No Connect. No Connect. Voltage Supply; 3.3V. Ground. Clock Output; 35.328 MHz. Pullable Crystal Input; 19.44 MHz. Pullable Crystal Output; 19.44 MHz. High = reference ICLK within range, Low = reference ICLK out of range. Ground. Voltage Supply; 3.3V. No Connect. No Connect. No Connect. No Connect. Pin Description Selector Guide Part Number Input Frequency Range Outputs 1 Output Frequencies 35.328 MHz CY26049ZC-4 Reference Input Clock:19.44 MHz Crystal: 19.44-MHz pullable crystal per Cypress specification Description CY26049-4 is a FailSafe frequency synthesizer with a reference clock input and 35.328-MHz output. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO, which serves as a primary clock source. The FailSafe control circuit synchronizes the DCXO oscillator with the reference as long as the reference is within the pull range of the crystal. In the event of a reference clock failure the DCXO maintains the last frequency of the reference clock. The unique feature of the CY26049-4 is that the DCXO is in fact the primary clocking source. When the reference clock is restored, the DCXO automatically resynchronizes to the reference. The status of the reference clock input, as detected by the CY26049-4, is reported by the SAFE pin. Document #: 38-07484 Rev. *A Page 2 of 6 ADVANCE INFORMATION Absolute Maximum Conditions Supply Voltage (VDD) ........................................-0.5 to +7.0V DC Input Voltage........................................ -0.5V to VDD+0.5 Storage Temperature (Non-condensing).....-55C to +125C CY26049-4 Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C.................................> 10 years Package Power Dissipation....................................... 350 mW ESD (Human Body Model) MIL-STD-883..................... 2000V (Above which the useful life may be impaired. For user guidelines, not tested.) Comments Parallel resonance, fundamental mode, AT cut Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed Min. - - - 3 - 400 - - 180 14.4 Typ. 19.44 14 - - 0.5 - - - - 18 Max. - - 25 - 2 - -200 7 250 21.6 fF mW ppm ppm pF Unit MHz pF Recommended Pullable Crystal Specifications[1] Parameter FNOM CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Third overtone separation from 3*FNOM High side Third overtone separation from 3*FNOM Low side Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance Recommended Operating Conditions Parameter VDD TAC CLOAD tpu Operating Voltage Ambient Temperature (Commercial Temperature) Max Output Load Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.15 0 - 0.05 Typ. 3.3 - - - Max. 3.45 70 15 500 Unit V C pF ms DC Electrical Specifications (Commercial Temp: 0 to 70C) Parameter IOH IOL VIH VIL IIH IIL CIN IDD Parameter fICLK-E LR DC = t2/t1 TPJIT1 t6 Description Output High Current Output Low Current Input High Voltage Input High Voltage Input High Current Input Low Current Input Capacitance Supply Current CLOAD = 15 pF, VDD = 3.45V Test Conditions Input Clock Frequency, External Mode Range of reference ICLK for Safe = High Duty Cycle defined in Figure 1, measured at 50% of VDD RMS Period Jitter, RMS PLL Lock Time Time for PLL to lock within 150 ppm of target frequency Notes: 1. Ecliptek ECX-5763-19.440M meets these specifications. 2. Dependent on crystals chosen and crystal specs. Test Conditions VOH = VDD - 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) CMOS Levels CMOS Levels VIH = VDD VIL = 0V Min. 12 12 0.7 - - - - - Typ. 24 24 - - 5 5 - - Max. - - - 0.3 10 10 7 30 Unit mA mA VDD VDD A A pF mA AC Electrical Specifications (Commercial Temp: 0 to 70 C) Description Frequency, Input Clock FailSafe Lock Range[2] Output Duty Cycle Min. - -250 45 - - - Typ. 19.44 - 50 - - - Max. Unit - 55 250 50 3 MHz % ps ps ms +250 ppm Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods Document #: 38-07484 Rev. *A Page 3 of 6 ADVANCE INFORMATION AC Electrical Specifications (Commercial Temp: 0 to 70 C) (continued) Parameter tfs_lock ferror ER EF Description FailSafe Lock Time Frequency Synthesis Error Rising Edge Rate Falling Edge Rate Test Conditions Time for PLL to lock to ICLK (outputs phase aligned with ICLK and Safe = High) Actual mean frequency error vs. target Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Min. - - 0.8 0.8 CY26049-4 Typ. - 0 1.4 1.4 Max. Unit 7 - 2 2 s ppm V/ns V/ns Voltage and Timing Definitions t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t3 80% CLK 20% t4 Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4 Test Circuit ICLK 1 2 3 4 16 15 14 13 VDD 5 12 VDD 0.1uF 6 11 10 9 0.1uF CLKA 7 CLOAD 8 19.44MHz Ordering Information Ordering Code CY26049ZC-4 CY26049ZC-4T Package Type 16-lead TSSOP 16-lead TSSOP--Tape and Reel Operating Temperature Range Commercial 0 to 70C Commercial 0 to 70C Document #: 38-07484 Rev. *A Page 4 of 6 ADVANCE INFORMATION Package Drawing and Dimensions 16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 CY26049-4 51-85091-** FailSafe and PacketClock are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07484 Rev. *A Page 5 of 6 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. ADVANCE INFORMATION Document History Page Document Title: CY26049-4 FailSafeTM PacketClockTM Global Communications Clock Driver Document Number: 38-07484 REV. ** *A ECN No. 119590 128090 Issue Date 11/01/02 9/11/03 Orig. of Change CKN IJA New Data Sheet Description of Change CY26049-4 Changed name from FailSafe Communications Clock Generator to FailSafe PacketClock Global Communications Clock Generator Changed wording in Features and Benefits and Pin Description table Replaced Recommended Pullable Crystal Specifications table Document #: 38-07484 Rev. *A Page 6 of 6 |
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